1. Field of the Invention
The present invention relates to a method of producing a nanocolumnar airbridge structure in a Very-Large Scale Integrated (VLSI) and Ultra-Large Scale Integrated (ULSI) device and high performance packaging. More particularly, the present invention relates to a nanocolumnar airbridge structure prepared by the method of the present invention.
2. Description of the Related Art
The fabrication of Very-Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated (ULSI) circuit requires metallic wiring, which connects individual devices in a semiconductor chip to one another. One method of creating such wiring network on such a small scale is the dual damascene (DD) process known in the art as shown schematically in FIGS. 1a through 1g. 
In a standard DD process, an interlayer dielectric (ILD), shown as two layers PA1-110, PA1-120 is coated on the substrate PA1-100, as shown in FIG. 1a. The via level dielectric PA1-110 and the line level dielectric PA1-120 are shown separately for clarity of the process flow description. In general, these two layers can be made of the same or different insulating films and in the former case applied as a single monolithic layer. A hard mask layer PA1-130 is optionally employed to facilitate etch selectivity and to serve as a polish stop as will be seen later.
The wiring interconnect network has two types of features: (1) line features that traverse a distance across the chip; and (2) via features, which connect lines in different levels together. Historically, both layers are made from an inorganic glass like silicon dioxide (SiO2) or a fluorinated silica film deposited by plasma enhanced chemical vapor deposition (PECVD).
In the dual damascene process, the position of the lines PA1-150 and the vias PA1-170 are defined lithographically in photoresist layers, PA1-140, as depicted in FIGS. 1b and 1d, and transferred into the hard mask and ILD layers using reactive ion etching processes. The process sequence shown in FIGS. 1a through 1g is called a Line-first approach because the trench PA1-160 which will house the line feature is etched first, as shown in FIG. 1c. After the trench formation, lithography is used to define a via pattern PA1-170 in the photoresist layer PA1-140, which is transferred into the dielectric material to generate a via opening PA1-180, as shown in FIG. 1d. 
The dual damascene trench and via structure PA1-190 is shown in FIG. 1e after the photoresist has been stripped. This structure PA1-190 is coated with a conducting liner material or material stack PA1-200, which serve to protect the conductor metal lines and vias. They also serve as an adhesion layer between the conductor and the ILD.
This recess is then filled with a conducting fill material PA1-210 over the surface of the patterned substrate. The fill is most commonly accomplished by electroplating of copper although other methods such as chemical vapor deposition (CVD) and other materials such as Al or Au can also be used. The fill and liner materials are then chemically-mechanically polished (CMP) to be coplanar with the surface of the hard mask. The structure at this stage is shown in FIG. 1f. 
A capping material PA1-220 is deposited over the metal or as a blanket film, as depicted in FIG. 1g, to passivate the exposed metal surface and to serve as a diffusion barrier between the metal and any additional ILD layers to be deposited over them. Silicon nitride, silicon carbide, and silicon carbonitride films deposited by PECVD are typically used as the capping material PA1-220. This process sequence is repeated for each level of the interconnects on the device. Since two interconnect features are defined to form a conductor inlay within an insulator by a single polish step, this process is designated a dual damascene process.
As with any circuit, semiconductor chips are prone to signal propagation delays which depend on the product of the line resistance, R, and the interconnect capacitance, C. In order to improve the performance of semiconductor chips, manufacturers have reduced the resistivity of the metal used in fabrication by replacing aluminum wiring by copper. By moving to lower dielectric constant (k) materials, manufacturers have also begun to reduce the capacitance, C, in the circuit.
The common terminology used to describe the dielectric films is to classify them as standard k (4.5<k<10), low k (k<3.0), ultra low k (2.0<k<2.5) and extreme low k (k<2.0). Ultra low k and extreme low k dielectrics generally tend to be porous with intentionally engineered voids in their structure. Since the lowest dielectric constant possible is defined by air or vacuum (kvac=1), many have developed means to produce voids in the dielectric. When the void volume extends and occupies substantial contiguous regions of the gaps between the lines one achieves an interconnect structure wherein the lines are nominally separated by a gas or vacuum as the ILD material. In the following descriptions the term air bridge is used to describe such an interconnect structure to distinguish it from structures wherein the ILD is porous with void volume dispersed randomly within a nominally contiguous solid dielectric.
One prior art approach to air bridge construction is shown in FIG. 2. In this process, a low-k structure is constructed after metal deposition steps to form the interconnects. For the purpose of reference, these types of processes are designated in the present application as Metal-then-Air Bridge (MAB) approaches consistent with the process sequence used.
Most processes that follow this approach begin with the standard DD fabrication sequence. Thus the process flow is consistent with FIGS. 1a through 1g. After the metallization step and before the cap layer deposition, a nanometer scale pattern is transferred into the underlaying interconnect structure and capped. Thus, for example, the structure shown in FIG. 2 is identical to the DD structure shown in FIG. 1f except the dielectric stack has nanocolumnar voids or pillars PA2-150 in the dielectric stack. Additional levels can then be fabricated in the same manner above the air bridge level.
One disadvantage of this approach is that exposure of the metallic line to harsh reactive ion etch processes is generally required in the step of patterning of the dielectric. Accordingly, an alternate approach that could circumvent the limitations of the MAB approaches would be highly desirable and beneficial in the fabrication of reliable multilevel air bridge structures.
The present invention provides such a method of producing a nanocolumnar airbridge structure in a Very-Large Scale Integrated (VLSI) and Ultra-Large Scale Integrated (ULSI) device and high performance packaging.